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78A207 MFR1 Receiver
April 2000
DESCRIPTION
The 78A207 is a single-chip, Multi-Frequency (MF) receiver that can detect all 15 tone-pairs, including ST and KP framing tones. This receiver is intended for use in equal access applications and thus meets both Bell and CCITT R1 central office register signaling specifications. The 78A207 employs state-of-the-art switched capacitor filters in CMOS technology. The receiver consists of a bank of channel-separation bandpass filters followed by zero-crossing detectors and frequency-measurement bandpass filters, an amplitude check circuit, a timer and decoder circuit, and a clock generator. The device does not attempt to identify strings of digits by the KP (key pulse) and ST (stop) tone pairs. No anti-alias filtering is needed if the input signal is band-limited to 26 KHz. The only external component required is an inexpensive television "color burst" 3.58 MHz crystal. The outputs interface directly with standard CMOS or TTL circuitry and are three-state enabled to facilitate bus-oriented architecture.
FEATURES
* * * * * * * * * Meets Bell and CCITT R1 specifications 20-pin plastic DIP Single low-tolerance 5V supply Detects all 15 tone-pairs including ST and KP Long KP capability Built-in amplitude discrimination Excellent noise tolerance Outputs in either "n of 6" or hexadecimal code Three-state outputs, CMOS-compatible and TTL-compatible
BLOCK DIAGRAM
700 VIN 900
700
THRESHOLD DETECTOR QUAL LOGIC R Q S
CSTR
DV
900
R 1100 1100 S Q DE
1300
1300 LKP
1500
1500
HEX QUAL
1700 PRE-FILTER X1 ZERO CROSSING DETECTORS
1700 BANDPASS FILTER D5 D4 D3 D2
X2
CLOCK GENERATOR
CHIP CLOCKS
D1 D0
XOUT VOLTAGE DIVIDER
VOLTAGE REF TONE DETECTOR
EN
AGN
VDD
DGND
78A207 MFR1 Receiver
FUNCTIONAL DESCRIPTION
VIN This pin accepts the analog input. It is internally biased to half the supply and is capacitively coupled to the channel separation filters. The input may be DC coupled as long as it does not exceed VDD or drop below GND. Equivalent input circuit is shown below in Figure 1. CRYSTAL OSCILLATOR The 78A207 contains an on-board inverter with sufficient gain to provide oscillation when connected to a low cost television "color-burst" crystal. The onchip clock signals are generated from the oscillator. The crystal is connected between X1 and X2. XOUT is a 3.58 MHz square wave capable of driving other circuits as long as the capacitive load does not exceed 50 pF. Other devices driven by XOUT should use X1 as the input pin, while X2 should be left floating. LKP The KP timer control: When high, the KP detect time is increased. When low, the KP detect time is the same as for other tones. QUAL Enables tone pair qualification. When low, the threshold detector outputs are passed to the data outputs (D0-D5) without validation in the format selected by the HEX pin. These outputs, plus strobes DV and DE, are updated once per 2.3 ms frame. Note that the strobes will cycle once per frame (even when the inputs are stable.) As always, data changes only when both strobes are low. CSTR This input clears both the DV and DE strobes, and is active low. After CSTR is released, the strobes will remain low until a new detect (or error) occurs. The output data is latched by CSTR and will not change while CSTR is low, even in the event that a new detect is qualified internally. (Note that improper use of CSTR may result in missed detects.) The outputs will be cleared to zero when no valid tone pair is present. For the "n of 6" mode, the HEX pin is pulled low, and each output represents one of the six frequencies as shown below: FREQUENCY 700 900 1100 1300 1500 1700 OUTPUT PIN D0 D1 D2 D3 D4 D5 EN EN The three-state enable control: When low, the D0D5 outputs are in the low impedance state. In an interrupt oriented microprocessor interface, EN and CSTR will often be tied together to provide automatic reset of the strobes when the output data is enabled. STROBE PINS - DV AND DE Valid data is indicated on the DV strobe pin, and data errors are indicated on the DE strobe pin. Whenever a valid 2 of 6 code has been detected, the DV strobe rises. It remains high until the code goes away, or the CSTR line is activated. When an invalid code is detected, e.g., 1 of 6, 3 of 6, etc., the DE strobe remains high until all errors stop, a valid tone pair is detected, or the CSTR line is activated. Once cleared by CSTR, DE will not reactivate until a new invalid condition is detected. The DE and DV strobes will never be high simultaneously. DATA OUTPUT MODES The digital output format may be either "n of 6" or 4bit hexadecimal. For "hex" mode, the HEX pin is pulled high. Outputs D0 to D3 provide a 4-bit code identifying one of the 15 valid tone combinations according to Table1.
The outputs will be cleared to zero when no valid tone is present.
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78A207 MFR1 Receiver
TABLE 1: Channels 0-1 0-2 1-2 0-3 1-3 2-3 0-4 1-4 2-4 3-4 2-5 4-5 1-5 3-5 0-5 Tone Pair Freq. 700, 900 700, 1100 900, 1100 700, 1300 900, 1300 1100, 1300 700, 1500 900, 1500 1100, 1500 1300, 1500 1100, 1700 1500, 1700 900, 1700 1300, 1700 700, 1700 any other signal NOTE: In the hex mode, D4 = DE and D5 = DV. Name 1 2 3 4 5 6 7 8 9 0 KP ST ST1 ST2 ST3 D3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 D2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 D1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
VDD
20 pF VIN 2 3 k VDD 200 k 3 k
GND
GND
FIGURE 1: VIN Equivalent Input Circuit
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78A207 MFR1 Receiver
TIMING SPECIFICATIONS PARAMETER Ton Ton Ton Ton Ton Ton Tpse Tbr Tsu Th Tstr Data Setup Time Data Hold Time Minimum Strobe Pulse Width QUAL High QUAL Low Tsep Minimum Strobe Separation QUAL High QUAL Low Tr Tf Tw Ten Tdis Trst Rise Time DV, DE, D0-D5 10-90% Fall Time DV, DE, D0-D5 10-90% CSTR Width Data Enable Time Data Disable Time Strobe Reset Time CL = 20 pF CL = 20 pF CL = 20 pF CL = 20 pF 50 100 100 100 20 2 100 100 ms ms ns ns ns ns ns ns 20 2 ms ms Pause Time Tone Time, All Others Tone Time, KP (LKP = DGND) Tone Time, KP (LKP = VDD) CONDITIONS detect reject detect reject detect reject detect reject 6 7 4 20 10 30 10 30 10 MIN 55 30 NOM MAX UNIT ms ms ms ms ms ms ms ms s s ms
Tskew Tone Skew Tolerance
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78A207 MFR1 Receiver
T BR TONE 1
T PSE
T SKEW T ON TONE 2
T SKEW D0-D5 T SU T STR DV (QUAL = 1) TH
DV (QUAL = 0) T STR T SEP
DE (QUAL = 0)
FIGURE 2: 78A207 Timing Diagram
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Operating above absolute maximum ratings may damage the device.) PARAMETER DC Supply Voltage VDD Operating Temperature Storage Temperature Power Dissipation (25C) (Derate above TA=25C @ 6.25 mW/C) Input Voltage DC Current into any input Lead Temperature (Soldering, 10 sec.) RATING + 7V 0 to 70 (Ambient)C 65 to 150C 650mW (VDD + 0.3V) to -0.3V 10mA 300C
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78A207 MFR1 Receiver
DC ELECTRICAL CHARACTERISTICS (0C TA 70C, VDD = 5V 10%) PARAMETER Idd Vol Supply Current Output Logic 0 Iol = 8 mA Iol = 1 mA Voh Output Logic 1 Ioh = -4 mA Ioh = -1 mA Vih Voh Zin Lin Input Logic 1 Input logic 0 Analog Input Impedance (Input between VDD and AGND) Digital Input Current (Input between VDD and DGND)
VDD-1.0 VDD-0.5
CONDITIONS
MIN
NOM
MAX 20 0.5 0.4
UNIT mA V V V V V
2.0 0.8
V
100K 30 pF
-50 50
A
AC CHARACTERISTICS (0C TA 70, VDD = 5V 10%) PARAMETER F A AN TW T3 N60 N180 Nn NI Frequency for Detect Tolerance Amplitude for Detect Amplitude for no Detect Twist Tolerance Third MF Tone Reject Amp 60 HZ Tolerance 180 HZ Tolerance Noise Tolerance1 Impulse Noise Tolerance2 each tone CONDITIONS MIN (0.015 xFo + 5) -25 0.123 0 2.191 -35 0.039 NOM MAX UNIT Hz dBm Vpp dB Vpp dB dB dBm Vpp dBm Vpp -20 +12 dB dB
TW=
high tone low tone
-6 -15 81 0.777 68 0.174
+6
relative to highest Amplitude tone not more than one error in 2500 10-digit calls same as above same as above same as above
NOTES: 1. C-message weighted. Measured with respect to highest amplitude tone. 2. With noise tape 201 per PUB 56201. Measured with respect to highest aplitude tone.
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78A207 MFR1 Receiver
MECHANICAL SPECIFICATIONS
20-Pin DIP
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78A207 MFR1 Receiver
PACKAGE PIN DESIGNATIONS
(Top View)
CAUTION: Use handling procedures necessary for a static sensitive component.
AGND VIN HEX QUAL LKP EN VDD D0 D1 D2
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
20-Pin DIP 78A207
XOUT X1 X2 CSTR DGND DV DE D5 D4 D3
ORDERING INFORMATION
PART DESCRIPTION 78A207 20-Pin Plastic DIP 78A207-CP 78A207-CP ORDER NUMBER PACKAGING MARK
No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK Semiconductor Corporation and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet is current before placing orders. TDK Semiconductor Corporation, 2642 Michelle Drive, Tustin, CA 92780-7019, (714) 508-8800, FAX: (714) 508-8877 (c)1989 TDK Semiconductor Corporation 04/24/00- rev. C
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